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HUFA75639G3, HUFA75639P3, HUFA75639S3S
Data Sheet December 2001
56A, 100V, 0.025 Ohm, N-Channel UltraFET Power MOSFETs
These N-Channel power MOSFETs are manufactured using the innovative UltraFET(R) process. This advanced process technology achieves the lowest possible on-resistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, lowvoltage bus switches, and power management in portable and battery-operated products. Formerly developmental type TA75639.
Features
* 56A, 100V * Simulation Models - Temperature Compensated PSPICE(R) and SABERTM Electrical Models - Spice and Saber Thermal Impedance Models - www.fairchildsemi.com * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards"
Symbol
D
Ordering Information
PART NUMBER HUFA75639G3 HUFA75639P3 HUFA75639S3S PACKAGE TO-247 TO-220AB TO-263AB BRAND 75639G 75639P 75639S
G
S
NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HUFA75639S3ST.
Packaging
JEDEC STYLE TO-247
SOURCE DRAIN GATE DRAIN (FLANGE)
JEDEC TO-220AB
SOURCE DRAIN GATE
DRAIN (TAB)
JEDEC TO-263AB
GATE SOURCE
DRAIN (FLANGE)
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy of the requirements, see AEC Q101 at: http://www.aecouncil.com/ Reliability data can be found at: http://www.fairchildsemi.com/products/discrete/reliability/index.html. All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
(c)2001 Fairchild Semiconductor Corporation HUFA75639G3, HUFA75639P3, HUFA75639S3S Rev. B
HUFA75639G3, HUFA75639P3, HUFA75639S3S
Absolute Maximum Ratings
TC = 25oC, Unless Otherwise Specified 100 100 20 56 Figure 4 Figures 6, 14, 15 200 1.35 -55 to 175 300 260 UNITS V V V A
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
W W/oC oC
oC oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. TJ = 25oC to 150oC.
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS
TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current
BVDSS IDSS
ID = 250A, VGS = 0V (Figure 11) VDS = 95V, VGS = 0V VDS = 90V, VGS = 0V, TC = 150oC
100 -
-
1 250 100
V A A nA
Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance THERMAL SPECIFICATIONS Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient
IGSS
VGS = 20V
VGS(TH) rDS(ON)
VGS = VDS, ID = 250A (Figure 10) ID = 56A, VGS = 10V (Figure 9)
2 -
0.021
4 0.025
V
RJC RJA
(Figure 3) TO-247 TO-220, TO-263
-
-
0.74 30 62
oC/W oC/W oC/W
SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 10V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge Qg(TOT) Qg(10) Qg(TH) Qgs Qgd VGS = 0V to 20V VGS = 0V to 10V VGS = 0V to 2V VDD = 50V, ID 56A, RL = 0.89 Ig(REF) = 1.0mA (Figure 13) 9.8 24 nC nC 110 57 3.7 130 75 4.5 nC nC nC tON td(ON) tr td(OFF) tf tOFF VDD = 50V, ID 56A, RL = 0.89, VGS = 10V, RGS = 5.1 15 60 20 25 110 70 ns ns ns ns ns ns
(c)2001 Fairchild Semiconductor Corporation
HUFA75639G3, HUFA75639P3, HUFA75639S3S Rev. B
HUFA75639G3, HUFA75639P3, HUFA75639S3S
Electrical Specifications
PARAMETER CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) 2000 500 65 pF pF pF TC = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = 56A ISD = 56A, dISD/dt = 100A/s ISD = 56A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP MAX 1.25 110 320 UNITS V ns nC
Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 175 TC , CASE TEMPERATURE (oC) 60 50 40 30 20 10 0 25 50 75 100 125 150 175 TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE
2 1 ZJC, NORMALIZED THERMAL IMPEDANCE DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-2 t, RECTANGULAR PULSE DURATION (s) 10-1 100 101
0.1
SINGLE PULSE 0.01 10-5 10-4 10-3
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
(c)2001 Fairchild Semiconductor Corporation
ID, DRAIN CURRENT (A)
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE
HUFA75639G3, HUFA75639P3, HUFA75639S3S Rev. B
HUFA75639G3, HUFA75639P3, HUFA75639S3S Typical Performance Curves
1000
(Continued)
TC = 25oC
IDM , PEAK CURRENT (A)
FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 175 - TC 150
100
VGS = 10V
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 t, PULSE WIDTH (s) 10-1 100 101
FIGURE 4. PEAK CURRENT CAPABILITY
1000 IAS, AVALANCHE CURRENT (A) TJ = MAX RATED TC = 25oC ID, DRAIN CURRENT (A)
300
If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100 STARTING TJ = 25oC STARTING TJ = 150oC
100 100s
10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10 VDS , DRAIN TO SOURCE VOLTAGE (V)
1ms VDSS(MAX) = 100V 10ms
100
200
10 0.001
0.01
0.1
1
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322. FIGURE 5. FORWARD BIAS SAFE OPERATING AREA FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY
100 VGS = 6V ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 80 VGS = 20V 60 VGS = 10V VGS = 7V
100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 175oC
80
60
40 VGS = 5V 20 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 0 1 2 3 4 5 6 7
40
20 25oC 0 0 1.5 3.0 4.5 6.0 7.5 VGS , GATE TO SOURCE VOLTAGE (V) -55oC
0
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS
(c)2001 Fairchild Semiconductor Corporation
HUFA75639G3, HUFA75639P3, HUFA75639S3S Rev. B
HUFA75639G3, HUFA75639P3, HUFA75639S3S Typical Performance Curves
3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 2.0 1.5 1.0 0.5 0 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) 0.6 -80 -40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 56A NORMALIZED GATE
(Continued)
1.2 VGS = VDS, ID = 250A THRESHOLD VOLTAGE
1.0
0.8
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A
3000 2500 C, CAPACITANCE (pF) VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD CISS 1500 1000 COSS 500 CRSS
1.1
2000
1.0
0.9 -80
0 -40 0 40 80 120 160 200 0 10 20 30 40 50 60 TJ , JUNCTION TEMPERATURE (oC) VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10 VGS , GATE TO SOURCE VOLTAGE (V)
8
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 56A ID = 37A ID = 18A 30 40 50 60
2 VDD = 50V 0 0 10 20
Qg, GATE CHARGE (nC)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
(c)2001 Fairchild Semiconductor Corporation
HUFA75639G3, HUFA75639P3, HUFA75639S3S Rev. B
HUFA75639G3, HUFA75639P3, HUFA75639S3S Test Circuits and Waveforms
VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD
+
-
0V
IAS 0.01
0 tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
VDS RL VDD VDS VGS = 20V VGS
+
Qg(TOT)
Qg(10) VDD VGS VGS = 2V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 10V
DUT IG(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORM
VDS
tON td(ON) RL VDS
+
tOFF td(OFF) tr tf 90%
90%
VGS
DUT RGS
VDD 0
10% 90%
10%
VGS VGS 0 10%
50% PULSE WIDTH
50%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. RESISTIVE SWITCHING WAVEFORMS
(c)2001 Fairchild Semiconductor Corporation
HUFA75639G3, HUFA75639P3, HUFA75639S3S Rev. B
HUFA75639G3, HUFA75639P3, HUFA75639S3S PSPICE Electrical Model
SUBCKT HUFA75639 2 1 3 ;
CA 12 8 2.8e-9 CB 15 14 2.65e-9 CIN 6 8 1.9e-9 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 110 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 LDRAIN 2 5 2e-9 LGATE 1 9 1e-9 LSOURCE 3 7 0.47e-9 RLGATE 1 9 10 RLDRAIN 2 5 20 RLSOURCE 3 7 4.69 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
12 LGATE GATE 1 RLGATE CIN ESG + EVTEMP RGATE + 18 22 9 20 DPLCAP 10 RSLC1 51 ESLC 50 EBREAK MWEAK MMED MSTRO LSOURCE 8 RSOURCE RLSOURCE S1A 13 8 S1B CA 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 RLDRAIN DBREAK 11 + 17 18 DBODY 5
rev Oct. 98
LDRAIN DRAIN 2
RSLC2
5 51
6 8 EVTHRES + 19 8 6
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.3e-2 RGATE 9 20 0.7 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*115),4))} .MODEL DBODYMOD D (IS = 1.4e-12 RS = 3.3e-3 XTI = 4.7 TRS1 = 2e-3 TRS2 = 0.1e-5 CJO = 3.3e-9 TT = 6.1e-8 M = 0.7) .MODEL DBREAKMOD D (RS = 3.5e- 1TRS1 = 1e- 3TRS2 = 1e-6) .MODEL DPLCAPMOD D (CJO = 2.2e- 9IS = 1e-3 0N = 10 M = 0.95 vj = 1.0) .MODEL MMEDMOD NMOS (VTO = 3.5 KP = 4.8 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u Rg = 0.7) .MODEL MSTROMOD NMOS (VTO = 3.97 KP = 56.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO =3.11 KP = 0.085 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 7 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 0.8e- 3TC2 = 1e-6) .MODEL RDRAINMOD RES (TC1 = 1e-2 TC2 = 1.75e-5) .MODEL RSLCMOD RES (TC1 = 2.8e-3 TC2 = 14e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC = -2.0e-3 TC2 = -1.75e-5) .MODEL RVTEMPMOD RES (TC1 = -2.75e- 3TC2 = 0.05e-9) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.0 VOFF = -3.5) VON = -3.5 VOFF = -6.0) VON = -2.5 VOFF = 4.95) VON = 4.95 VOFF = -2.5)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
(c)2001 Fairchild Semiconductor Corporation
+
-
RDRAIN 21 16
-
VBAT +
8 22 RVTHRES
HUFA75639G3, HUFA75639P3, HUFA75639S3S Rev. B
HUFA75639G3, HUFA75639P3, HUFA75639S3S SABER Electrical Model
nom temp=25 deg c 100v Ultrafet
REV Oct. 98 template HUFA75639 n2,n1,n3 electrical n2,n1,n3 { var i iscl d..model dbodymod = (is=1.4e-12, xti=4.7, cjo=33e-10,tt=6.1e-8, m=0.7) d..model dbreakmod = () d..model dplcapmod = (cjo=22e-10,is=1e-30,n=10,m=0.95, vj=1.0) m..model mmedmod = (type=_n,vto=3.5,kp=4.8,is=1e-30, tox=1) m..model mstrongmod = (type=_n,vto=3.97,kp=56.5,is=1e-30, tox=1) m..model mweakmod = (type=_n,vto=3.11,kp=0.085,is=1e-30, tox=1) sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-6.0,voff=-3.5) sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3.5,voff=-6.0) sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2.5,voff=4.95) sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=4.95,voff=-2.5)
ESG
LDRAIN DPLCAP 10 RSLC1 51 RSLC2 ISCL RLDRAIN RDBREAK 72 DBREAK 11 MWEAK DBODY MMED MSTRO CIN 8 EBREAK + 17 18 71 RDBODY 5 DRAIN 2
6 8 + EVTHRES + 19 8 6
50 RDRAIN 21 16
c.ca n12 n8 = 28.5e-10 c.cb n15 n14 = 26.5e-10 c.cin n6 n8 = 19e-10 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod i.it n8 n17 = 1 l.ldrain n2 n5 = 2.0e-9 l.lgate n1 n9 = 1e-9 l.lsource n3 n7 = 4.69e-10
GATE 1
LGATE
EVTEMP RGATE + 18 22 9 20
RLGATE
RSOURCE
LSOURCE 7 RLSOURCE SOURCE 3
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
RBREAK 18 RVTEMP 19
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=0.8e-3,tc2=-1e-6 res.rdbody n71 n5 = 3.3e-3, tc1=2.0e-3, tc2=0.1e-5 res.rdbreak n72 n5 = 3.5e-1, tc1=1e-3, tc2=1e-6 res.rdrain n50 n16 = 13e-3, tc1=1e-2,tc2=1.75e-5 res.rgate n9 n20 = 0.7 res.rldrain n2 n5 = 20 res.rlgate n1 n9 = 10 res.rlsource n3 n7 = 4.69 res.rslc1 n5 n51 = 1e-6, tc1=2.8e-3,tc2=14e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 4.5e-3, tc1=0,tc2=0 res.rvtemp n18 n19 = 1, tc1=-2.75e-3,tc2=0.05e-9 res.rvthres n22 n8 = 1, tc1=-2e-3,tc2=-1.75e-5 spe.ebreak n11 n7 n17 n18 = 110 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
VBAT +
-
-
8 22 RVTHRES
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/115))** 4)) } }
(c)2001 Fairchild Semiconductor Corporation
HUFA75639G3, HUFA75639P3, HUFA75639S3S Rev. B
HUFA75639G3, HUFA75639P3, HUFA75639S3S Spice Thermal Model
REV APRIL 1998 HUFA75639 CTHERM1 TH 6 2.8e-3 CTHERM2 6 5 4.6e-3 CTHERM3 5 4 5.5e-3 CTHERM4 4 3 9.2e-3 CTHERM5 3 2 1.7e-2 CTHERM6 2 TL 4.3e-2 RTHERM1 TH 6 5.0e-4 RTHERM2 6 5 1.5e-3 RTHERM3 5 4 2.0e-2 RTHERM4 4 3 9.0e-2 RTHERM5 3 2 1.9e-1 RTHERM6 2 TL 2.9e-1
RTHERM1 CTHERM1 TH JUNCTION
6
RTHERM2
CTHERM2
5
RTHERM3
CTHERM3
Saber Thermal Model
Saber thermal model HUFA75639 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 2.8e-3 ctherm.ctherm2 6 5 = 4.6e-3 ctherm.ctherm3 5 4 = 5.5e-3 ctherm.ctherm4 4 3 = 9.2e-3 ctherm.ctherm5 3 2 = 1.7e-2 ctherm.ctherm6 2 tl = 4.3e-2 rtherm.rtherm1 th 6 = 5.0e-4 rtherm.rtherm2 6 5 = 1.5e-3 rtherm.rtherm3 5 4 = 2.0e-2 rtherm.rtherm4 4 3 = 9.0e-2 rtherm.rtherm5 3 2 = 1.9e-1 rtherm.rtherm6 2 tl = 2.9e-1 }
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
TL
CASE
(c)2001 Fairchild Semiconductor Corporation
HUFA75639G3, HUFA75639P3, HUFA75639S3S Rev. B
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.
ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM
DISCLAIMER
FAST (R) FASTrTM FRFETTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MicroPakTM MICROWIRETM
OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM Power247TM PowerTrench (R) QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER (R)
SMART STARTTM STAR*POWERTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM TruTranslationTM UHCTM UltraFET (R)
VCXTM
STAR*POWER is used under license
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
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Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. H4

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Price & Availability of HUFA75639G3

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